The present invention is directed to decoder circuits, and more particularly to a 1-of-N decoder that places a predetermined binary level signal on one of a multiplicity of output lines in response to a multibit input signal.
Decoders of this type are commonly used to address random access and read only memories. To address the cells in a particular row of the memory, a word line connected to all of the cells in that row is brought to a predetermined binary state, e.g., high. All of the other word lines connected to the remaining rows of cells of the memory remain in a binary low state, so that only the information stored in the selected row of cells will be sensed through bit lines connected to the respective columns of cells. The 1-of-N decoder serves to bring the selected word line to the binary high state in response to an address word from a control CPU or the like.
In the past, standard decoder circuits have generally fallen into one of two categories. One category of decoders is comprised of only bipolar transistors using emitter coupled logic. The other category of decoders employs field effect transistors. Decoders in this latter category can be comprised entirely of field effect transistors, e.g., CMOS circuit arrangements, or a combination of bipolar NPN transistors with both N- and P-channel MOS transistors, i.e., BICMOS circuits.
Each of the two categories of decoder circuits has its attendant advantages and limitations. For example, the decoders which use MOS devices have essentially no static power dissipation, since current is drawn only when switching from one state to another. In contrast, the ECL decoder draws a much more significant current even while it is in an idle state.
However, decoders which use BICMOS technology are more expensive to manufacture because they require more masking steps to provide each of the bipolar NPN transistors, PMOS and NMOS field effect transistors during the fabrication of the integrated circuit. In addition, they must be fed with standard CMOS voltage levels, which are higher than those needed in the strictly bipolar approach.
Another advantage which the ECL decoder attains over the known FET-based circuits pertains to the output signal reference levels. In the bipolar ECL approach, the binary level signals on the output lines are referenced only to a single power source voltage. For example, a logic high signal might be at or quite near the higher power source voltage, and logic low might be a predetermined voltage below the high level. In contrast, the logic signals that are produced with the MOS decoder circuits are a function of both the high and low power supply levels. In other words, the logic high signal follows the higher power source voltage (e.g., V.sub.cc) and the logic low follows the ground reference voltage. A problem associated with this latter arrangement is that transient signals, i.e., logic swings, are dependent upon power supply noise and voltage variations.